The present invention relates to a method and/or architecture for simultaneous cross-port word size multiplication generally and, more particularly, to a method and/or architecture for simultaneous cross-port word size multiplication and high speed cycling through core areas.
Conventional approaches for cross-port word size multiplication use one or more of the following:
A) cross-port word size multiplication requiring active use of the address bus;
B) cycling through limited core areas requiring either active use of the address bus or special test modes; and
C) flagging a wraparound or last-state-in-sequence event for limited core area cycling could be done with on-chip logic only for a predetermined limited number of core areas.
U.S. Pat. No. 6,166,989 entitled Clock Synchronous Type Semiconductor Memory Device that can switch word configuration (Hamamoto, et al.) includes a mask control circuit used to inactivate the read or write data drivers during a specific operation mode.
Typical cross-port word size multiplication schemes use cascaded counter sections to separately cycle through predetermined blocks of addresses. Typical cross-port word size multiplication schemes also implement a number of control signals in order to permanently disable one (or several) MSBs of an address counter/register, thus reducing the addressable memory size. Conventional approaches have one or more of the following disadvantages:
(A) cross-port word size multiplication could not be done by straight address incrementation or decrementation using a dedicated control pin, and as such required active use of the address bus;
(B) did not allow cycling through reduced core areas without the need for active use of the address bus or special test modes, which most often are not available to the user; and
(C) reduced flexibility for isolating limited memory blocks and cycling through them without active address bus usage even using test modes.
Mask signals are used to mask data values either input to or output from the memory device, or as soon as they are read out of the memory cells. Such approaches can be found in the following U.S. Pat. No.: 6,175,534, filed Apr. 26, 1999; U.S. Pat. No. 6,175,514, filed Aug. 27, 1999; U.S. Pat. No. 6,170,034, filed Mar. 31, 1998; U.S. Pat. No. 6,167,487, filed Jan. 13, 1998; U.S. Pat. No. 6,166,989, filed Mar. 3, 1999.
U.S. Pat. No. 6,175,534 entitled Synchronous Semiconductor Storage Device (Taniguchi, et al.) uses a mask signal that can mask data values input to or output from the synchronous semiconductor storage device.
U.S. Pat. No. 6,175,514 entitled Content Addressable Memory Device (Henderson, et al.) discloses the memory device is able to activate a mask function, used in comparing/matching the outputs of two memory cells fed into a compare cell.
U.S. Pat. No. 6,170,034 entitled Hardware Assisted Mask Read/Write (WestonLewis, et al.) uses a mask bit counter which is incremented to point and allow processing of successive bits of a mask command stored in a mask word register.
U.S. Pat. No. 6,167,487 entitled Multiport RAM Having Functionally Identical Ports (Camacho, et al.) makes use of a pair of mask control signals for performing byte masking of the input data.
The present invention concerns an apparatus comprising a control circuit and a generation circuit. The control circuit may be configured to generate a mask signal, a unique counter control signal, and an incremented state signal in response to an address signal and a counter control signal. The generation circuit may (i) comprise an internal counter register and (ii) be configured to generate an output address in response to the mask signal, the unique counter control signal, and the incremented state signal. The mask signal may be configured to selectively mask the internal counter register.
The objects, features and advantages of the present invention include providing a method and apparatus for fast limited core area access and cross-port word size multiplication in synchronous multiport memories that may (i) implement a special-definition mask register associated with a mask-controlled incrementer/decrementer in order to restrict counter rank manipulation, (ii) selectively mask an internal address counter register, (iii) allow a number of features without active use of the address bus (during normal operation or silicon debug phase), (iv) provide high speed cycling through a limited memory area, (v) group ports to allow simultaneous fast access from one or more microprocessors, and/or (vi) address counter wraparound or last-state-in-sequence flagging.